Conventionally, as the circuit for generating clocks of a plurality of different frequencies, the circuit is known for employing a PLL (Phase Locked Loop) circuit etc. to produce the clock of which the frequency is a least common multiple thereof, and to de-multiply it by an appropriate ratio, thereby to generate a clock signal of a desired frequency. On the other hand, in some cases, coexistence of many kinds of frequencies is necessitated, depending upon the circumstances of various specifications or the like.
In such a case, in a prior art, the clocks of many kinds of frequencies are obtained by preparing a clock signal of a high frequency to de-multiply it. For example, in a case where clocks of 400 MHz and 500 MHz are required, a clock of which the frequency is 2 GHz, being a least common multiple thereof, is generated, and this clock of 2 GHz is de-multiplied by five and four, thereby to generate the clock of 400 MHz and the clock of 500 MHz, respectively.
The circuit for generating the clock of 2 GHz, however, is very difficult to realize, for example, by means of a device such as a CMOS of 0.4 μm. For this, there is a necessity for independently having the PLL circuit of 400 MHz and the PLL circuit of 500 MHz, respectively. This gives rise to a defect of incurring occurrence of interference between the PLL circuit companions, an increase in a consumption of the electric current due to having two PPL circuits, an augment in an layout size, or the like.
In addition hereto, switching the operational frequency with the PLL circuit requires a switching time of several to several hundreds of μs, which gives rise to a defect that an operation of the clock circuit becomes unstable during its time.
Thereupon, the clock generating circuit that can obtain an output of the clock of a desired frequency without incurring an increase in both consumption electric power and chip size has been proposed (For example, Patent document 1).
The clock generating circuit described in this patent document 1, as shown in FIG. 22, is configured of a multi-phase clock generating circuit 110 which generates a multi-phase clock of a fixed frequency from a single-phase clock, pulse generating circuits 120-1 to 120-n which generate non-overlapped pulses p0 to pn each of which does not overlap with the other by using one part of the multi-phase clock generated by the multi-phase clock generating circuit 110, and an or circuit 130 which computes a logical sum of a plurality of non-overlapped pulses p0 to pn produced by the pulse generating circuits 120-1 to 120-n. 
Upon explaining an actual operation, in a case of producing, for example, an eight-phase clock signal of a frequency of 250 MHz by the multi-phase clock generating circuit 110, the frequency of the clock, which is obtained by selecting the pulses that are obtained from the pulse generating circuits 120-1 to 120-n without causing them to overlap with each other, becomes 2 GHz, 1 GHz, 666 MHz, 500 MHz . . . .
Patent document 1: JP-P2001-209454A